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vcxo-to-lvcmos outputs ics81006i idt ? / ics ? vcxo-to-lvcmos outputs 1 ics81006aki rev. b october 8, 2008 vcxo 0: 1 1: 2 sync sync lp filter g eneral d escription the ics81006i is a high performance, low jitter/ low phase noise vcxo and is a member of the hiperclocks? family of high performance clock solutions from idt. the ics81006i works in conjunction with a pullable crystal to generate an output clock over the range of 12mhz - 31.25mhz and has 6 lvcmos outputs, effectively integrating a fanout buffer function. the frequency of the vcxo is adjusted by the vc control voltage input. the output range is 100ppm around the nominal crystal frequency. the vc control voltage range is 0 - v dd . the device is packaged in a small 4mm x 4mm vfqfn package and is ideal for use on space constrained boards typically encountered in adsl/vdsl applications. f eatures ? six lvcmos/lvttl outputs, 20 nominal output impedance ? output q5 can be selected for 1 or 2 frequency relative to the crystal frequency ? output frequency range: 12mhz to 31.25mhz ? crystal pull range: 90ppm (typical) ? synchronous output enable places outputs in high-imped- ance state ? on-chip filter on vin to suppress noise modulation of vcxo ? v dd /v ddo combinations 3.3v/3.3v 3.3v/2.5v 3.3v/1.8v 2.5v/2.5v 2.5v/1.8v ? 4mm x 4mm 20 lead vfqfn package is ideal for space constrained designs ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s b lock d iagram p in a ssignment oe0 vc xtal_in xtal_out div_sel_q5 oe1 q0 q1 q2 q3 q4 q5 (pullup) (pulldown) xtal_in xtal_out v dd vc div_sel_q5 gnd q2 v ddo q3 gnd oe1 gnd q5 v ddo q4 oe0 gnd q0 v ddo q1 1 2 3 4 5 20 19 18 17 16 ics81006i 20-lead vfqfn 4mm x 4mm x 0.925 package body k package top view 6 7 8 9 10 15 14 13 12 11 (pullup)
idt ? / ics ? vcxo-to-lvcmos outputs 2 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs t able 2. p in c haracteristics t able 1. p in d escriptions l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i1 e o , 0 e o4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p v d d v = o d d v 5 6 4 . 3 =3f p v d d , v 5 2 6 . 2 r o v 5 6 4 . 3 = v o d d v 5 2 6 . 2 = 4f p v d d , v 5 2 6 . 2 r o v 5 6 4 . 3 = v o d d v 2 = 6f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r t u o e c n a d e p m i t u p t u o v o d d v 3 . 3 =0 2 v o d d v 5 . 2 =5 2 v o d d v 8 . 1 =8 3 r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 1 , n i _ l a t x t u o _ l a t x t u p n i . t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x 3v d d r e w o p. n i p y l p p u s e v i t i s o p 4c vt u p n i. t u p n i e g a t l o v l o r t n o c 55 q _ l e s _ v i dt u p n in w o d l l u p , h g i h n e h w . 1 , w o l n e h w . t u p t u o 5 q r o f n i p t c e l e s r e d i v i d t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . 2 61 e ot u p n ip u l l u p , w o l n e h w . d e l b a n e s i t u p t u o 5 q , h g i h n e h w . n i p e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e t a t s e c n a d e p m i h g i h a o t 5 q s e c r o f 9 1 , 5 1 , 1 1 , 7d n gr e w o p. d n u o r g y l p p u s r e w o p , 2 1 , 0 1 , 8 8 1 , 6 1 , 4 1 , 3 q , 4 q , 5 q 0 q , 1 q , 2 q t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o k c o l c d e d n e - e l g n i s 0 2 . e c n a d e p m i t u p t u o 7 1 , 3 1 , 9v o d d r e w o p. s n i p y l p p u s t u p t u o 0 20 e ot u p n ip u l l u p . d e l b a n e e r a s t u p t u o 4 q : 0 q , h g i h n e h w . n i p e l b a n e t u p t u o . e t a t s e c n a d e p m i h g i h a o t 4 q : 0 q s e c r o f , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
idt ? / ics ? vcxo-to-lvcmos outputs 3 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 60.4c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 3a. p ower s upply dc c haracteristics , v dd = 3.3v5%, v ddo = 3.3v5% = 2.5v5% = 1.8v0.2v, t a = -40c to 85c t able 3b. p ower s upply dc c haracteristics , v dd = 2.5v5%, v ddo = 2.5v5% = 1.8v0.2v, t a = -40c to 85c t able 3c. lvcmos/lvttl dc c haracteristics , t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i v d d % 5 v 3 . 3 =2v d d 3 . 0 +v v d d % 5 v 5 . 2 =7 . 1v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i , 1 e o , 0 e o 5 q _ l e s _ v i d v d d % 5 v 3 . 3 =3 . 0 -8 . 0v v d d % 5 v 5 . 2 =3 . 0 -7 . 0v c ve g a t l o v l o r t n o c o x c v 0v d d v i h i t n e r r u c h g i h t u p n i 5 q _ l e s _ v i dv d d % 5 v 5 . 2 r o v 3 . 3 =0 5 1a 1 e o , 0 e ov d d % 5 v 5 . 2 r o v 3 . 3 =5a i l i t n e r r u c w o l t u p n i 5 q _ l e s _ v i dv d d % 5 v 5 . 2 r o v 3 . 3 =5 -a 1 e o , 0 e ov d d % 5 v 5 . 2 r o v 3 . 3 =0 5 1 -a i i n i p c v f o t n e r r u c t u p n iv d d v 5 2 6 . 2 r o v 5 6 4 . 3 =0 0 1 -0 0 1a v h o ; e g a t l o v h g i h t u p t u o1 e t o n v o d d % 5 v 3 . 3 =6 . 2v v o d d % 5 v 5 . 2 =8 . 1v v o d d v 2 . 0 v 8 . 1 =5 . 1v v l o ; e g a t l o v w o l t u p t u o1 e t o n v o d d % 5 v 5 . 2 r o v 3 . 3 =5 . 0v v o d d v 2 . 0 v 8 . 1 =4 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o d d . s m a r g a i d " t i u c r i c t s e t d a o l " , n o i t c e s t n e m e r u s a e m r e t e m a r a p e e s . 2 / l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v 5 7 3 . 25 . 25 2 6 . 2v 6 . 18 . 10 . 2v i d d t n e r r u c y l p p u s r e w o p 0 5a m i o d d t n e r r u c y l p p u s t u p t u o 0 2a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 25 . 25 2 6 . 2v v o d d e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v 6 . 18 . 10 . 2v i d d t n e r r u c y l p p u s r e w o p 0 5a m i o d d t n e r r u c y l p p u s t u p t u o 0 2a m
idt ? / ics ? vcxo-to-lvcmos outputs 4 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs t able 4a. ac c haracteristics , v dd = v ddo = 3.3v5%, t a = -40c to 85c t able 4b. ac c haracteristics , v dd = 3.3v5%, v ddo = 2.5v5%, t a = -40c to 85c t able 4c. ac c haracteristics , v dd = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 2 14 4 . 9 15 2 . 1 3z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n z h m 1 - z h k 1 : e g n a r n o i t a r g e t n i5 3 . 0s p ) o ( k s t ; w e k s t u p t u o 3 , 2 e t o n 4 q : 0 q 0 3s p 5 q : 0 q1 = 5 q _ l e s _ v i d0 0 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 5 7s p c d oe l c y c y t u d t u p t u o 4 46 5% . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 2 14 4 . 9 15 2 . 1 3z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n z h m 1 - z h k 1 : e g n a r n o i t a r g e t n i8 3 . 0s p ) o ( k s t ; w e k s t u p t u o 3 , 2 e t o n 4 q : 0 q 0 2s p 5 q : 0 q1 = 5 q _ l e s _ v i d0 9s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 8s p c d oe l c y c y t u d t u p t u o 5 45 5% . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 2 14 4 . 9 15 2 . 1 3z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n z h m 1 - z h k 1 : e g n a r n o i t a r g e t n i7 2 . 0s p ) o ( k s t ; w e k s t u p t u o 3 , 2 e t o n 4 q : 0 q 0 5s p 5 q : 0 q1 = 5 q _ l e s _ v i d0 8 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 40 0 4 1s p c d oe l c y c y t u d t u p t u o 5 45 5% . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
idt ? / ics ? vcxo-to-lvcmos outputs 5 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs t able 4d. ac c haracteristics , v dd = v ddo = 2.5v5%, t a = -40c to 85c t able 4e. ac c haracteristics , v dd = 2.5v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 2 14 4 . 9 15 2 . 1 3z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n z h m 1 - z h k 1 : e g n a r n o i t a r g e t n i8 2 . 0s p ) o ( k s t ; w e k s t u p t u o 3 , 2 e t o n 4 q : 0 q 5 2s p 5 q : 0 q1 = 5 q _ l e s _ v i d5 0 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 8s p c d oe l c y c y t u d t u p t u o 5 45 5% . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 2 14 4 . 9 15 2 . 1 3z h m t ) ? ( t i j ; ) m o d n a r ( r e t t i j e s a h p s m r 1 e t o n z h m 1 - z h k 1 : e g n a r n o i t a r g e t n i6 2 . 0s p ) o ( k s t ; w e k s t u p t u o 3 , 2 e t o n 4 q : 0 q 0 4s p 5 q : 0 q1 = 5 q _ l e s _ v i d5 8 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 40 0 4 1s p c d oe l c y c y t u d t u p t u o 0 40 6% . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
idt ? / ics ? vcxo-to-lvcmos outputs 6 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs t ypical p hase n oise at 19.44mh z @ 3.3v c ore /3.3v o utput 19.44mhz rms phase jitter (random) 1khz to 1mhz = 0.35ps (typical) o ffset f requency (h z ) dbc hz n oise p ower 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m
idt ? / ics ? vcxo-to-lvcmos outputs 7 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs p arameter m easurement i nformation scope qx lvcmos gnd 3.3v c ore /2.5v o utput l oad ac t est c ircuit 2.05v5% v ddo -1.25v5% v dd 1.25v5% 3.3v c ore /3.3v o utput l oad ac t est c ircuit scope qx lvcmos gnd 1.65v5% -1.65v5% v dd , v ddo 3.3v c ore /1.8v o utput l oad ac t est c ircuit 2.5v c ore /2.5v o utput l oad ac t est c ircuit 2.5 c ore /1.8v o utput l oad ac t est c ircuit rms p hase j itter scope qx lvcmos gnd 2.4v0.065v v ddo -0.9v0.1v v dd 0.9v0.1v scope qx lvcmos gnd 1.25v5% -1.25v5% v dd , v ddo phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power scope qx lvcmos gnd 1.6v0.025v v ddo -0.9v0.1v v dd 0.9v0.1v
idt ? / ics ? vcxo-to-lvcmos outputs 8 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs o utput r ise /f all t ime o utput s kew t period t pw t period odc = v dd 2 x 100% t pw q0:q5 o utput d uty c ycle /p ulse w idth /p eriod t sk(o) v ddo 2 v ddo 2 qy qx 20% 80% 80% 20% t r t f q0:q5
idt ? / ics ? vcxo-to-lvcmos outputs 9 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs a pplication i nformation oscillator f igure 1: vcxo o scillator c ircuit v c c v c s1 c l1 c s2 c l2 c v xtal vcxo (internal) optional ? ? ? ? ? control voltage t able 5. e xample c rystal p arameters l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n y c n e u q e r f l a n i m o n 4 4 . 9 1z h m f t e c n a r e l o t y c n e u q e r f 0 2 m p p f s y t i l i b a t s y c n e u q e r f 0 2 m p p e g n a r e r u t a r e p m e t g n i t a r e p o 00 7c c l e c n a t i c a p a c d a o l 2 1f p c o e c n a t i c a p a c t n u h s 4f p c , 0 c 1 o i t a r y t i l i b a l l u p 0 2 20 4 2 r s ee c n a t s i s e r s e i r e s t n e l a v i u q e 0 2 l e v e l e v i r d 1w m c 5 2 @ g n i g a r a e y r e p 3 m p p n o i t a r e p o f o e d o m l a t n e m a d n u f vcxo c rystal s election choosing a crystal with the correct characteristics is one of the most critical steps in using a voltage controlled crystal oscillator (vcxo). the crystal parameters affect the tuning range and v c control voltage used to tune frequency c v varactor capacitance, varies due to the change in control voltage accuracy of a vcxo. below are the key variables and an example of using the crystal parameters to calculate the tuning range of the vcxo. c l1, c l2 load tuning capacitance used for fine tuning or centering nominal frequency c s1, c s2 stray capacitance caused by pads, vias, and other board parasitics
idt ? / ics ? vcxo-to-lvcmos outputs 10 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c w o l _ v e c n a t i c a p a c r o t c a r a v w o lv c v 0 =4 . 5 1f p c h g i h _ v e c n a t i c a p a c r o t c a r a v h g i hv c v 3 . 3 =6 . 9 2f p t able 6. v aractor p arameters f ormulas ( ) ( ) ()( ) low v s l low v s l low v s l low v s l low c c c c c c c c c c c c c _ 2 2 _ 1 1 _ 2 2 _ 1 1 + + + + + + + ? + + = ( ) ( ) ()( ) high v s l high v s l high v s l high v s l high c c c c c c c c c c c c c _ 2 2 _ 1 1 _ 2 2 _ 1 1 + + + + + + + ? + + = 6 0 1 0 0 1 0 10 1 2 1 1 2 1 ) ( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? + ? ? = c c c c c c c c tpr range pull total high low ?c low is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance. c low determines the high frequency component on the tpr. ?c high is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance. c high determines the low frequency component on the tpr. absolute pull range (apr) = total pull range ? (frequency tolerance + frequency stability + aging) e xample c alculations using the tables and figures above, we can now calculate the tpr and apr of the vcxo using the example crystal parameters. for the numerical example below there were some assumptions made. first, the stray capacitance (c s1 , c s2 ), which is all the excess capacitance due to board parasitic, is 4pf. second, the expected lifetime of the project is 5 years; hence the inaccuracy due to aging is 15ppm. third, though many boards will not require load tuning capacitors (c l1 , c l2 ), it is recommended for long-term consistent performance of the system that two tuning capacitor pads be placed into every design. typical values for the load tuning capacitors will range from 0 to 4pf. ()() ()() pf pf pf pf pf pf pf pf pf c low 7 . 9 4 . 15 4 0 4 . 15 4 0 4 . 15 4 0 4 . 15 4 0 = + + + + + + + ? + + = ()() ()() pf pf pf pf pf pf pf pf pf c high 8 . 16 6 . 29 4 0 6 . 29 4 0 6 . 29 4 0 6 . 29 4 0 = + + + + + + + ? + + = ppm pf pf pf pf tpr 5 . 226 10 4 8 . 16 1 220 2 1 4 7 . 9 1 220 2 1 6 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? + ? ? = tpr = 113.25ppm apr = 113.25ppm ? (20ppm + 20ppm + 15ppm) = 58.25ppm the example above will ensure a total pull range of 113.25 ppm with an apr of 58.25ppm. many times, board designers may select their own crystal based on their application. if the application requires a tighter apr, a crystal with better pullability (c0/c1 ratio) can be used. also, with the equations above, one can vary the frequency tolerance, temperature stability, and aging or shunt capacitance to achieve the required pullability.
idt ? / ics ? vcxo-to-lvcmos outputs 11 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs s chematic e xample figure 2 shows an example of ics81006i application schematic. the decoupling capacitors should be located as close as possible to the power pin. for the lvcmos 20 output drivers, series termination example is shown in the schematic. additional termination approaches are shown in the lvcmos termination application note. f igure 2. ics81006i s chematic e xample i nputs : c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. the vc pin can not be floated. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utput : all unused lvcmos output can be left floating. we recommend that there is no trace attached. c2 spare r5 1k vc = 0v to vdd vdd c1 spare u1 81006 2 3 4 5 6 7 8 9 11 12 13 14 17 18 19 20 10 16 15 1 xtal_out vdd vc div_sel_q5 oe1 gnd q5 vddo gnd q3 vddo q2 vddo q0 gnd oe0 q4 q1 gnd xtal_in zo = 50 (u1-13) c3 0.1uf unused outputs can be left floating. there should be no trace attached to unused outputs. device characterized and specification limits set with all outputs terminated. c6 0.1uf c5 0.1uf c7 10uf pull-up example (u1-9) r4 1k quartz crystal should be placed as close to the device as possible. vddo pull-down example vdd r3 1k vddo r1 30 vdd r2 30 vc c4 0.1uf xta l (u1-17) zo = 50 vdd (u1-3) 81006i
idt ? / ics ? vcxo-to-lvcmos outputs 12 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs f igure 3. p.c.a ssembly for e xposed p ad t hermal r elease p ath ?s ide v iew (d rawing not to s cale ) vfqfn epad t hermal r elease p ath in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadfame base package, amkor technology. thermal via land pattern solder pin solder pin pad pin pad pin ground plane exposed heat slug (ground pad)
idt ? / ics ? vcxo-to-lvcmos outputs 13 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs r eliability i nformation t ransistor c ount the transistor count for ics81006i is: 983 t able 7. ja vs . a ir f low t able for 20 l ead vfqfn ja by velocity (meters per second) 013 multi-layer pcb, jedec standard test boards 60.4c/w 52.8c/w 46.0c/w
idt ? / ics ? vcxo-to-lvcmos outputs 14 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs t able 8. p ackage d imensions for 20 l ead vfqfn p ackage o utline - k s uffix for 20 l ead vfqfn n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y sm u m i n i mm u m i x a m n 0 2 a 0 8 . 00 . 1 1 a 05 0 . 0 3 a e c n e r e f e r 5 2 . 0 b 8 1 . 00 3 . 0 e c i s a b 0 5 . 0 n d 5 n e 5 d 0 . 4 2 d 5 7 . 00 8 . 2 e 0 . 4 2 e 5 7 . 00 8 . 2 l 5 3 . 05 7 . 0 reference document: jedec publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this draw- ing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 6 below.
idt ? / ics ? vcxo-to-lvcmos outputs 15 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 9. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i k a 6 0 0 1 8i a 6 0 0 1n f q f v d a e l 0 2e b u tc 5 8 o t c 0 4 - t i k a 6 0 0 1 8i a 6 0 0 1n f q f v d a e l 0 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i k a 6 0 0 1 8l i a 6 0 0n f q f v " e e r f - d a e l " d a e l 0 2e b u tc 5 8 o t c 0 4 - t f l i k a 6 0 0 1 8l i a 6 0 0n f q f v " e e r f - d a e l " d a e l 0 2l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
idt ? / ics ? vcxo-to-lvcmos outputs 16 ics81006aki rev. b october 8, 2008 ics81006i vcxo-to-6 lvcmos outputs t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d bd 4 t - a 4 t 9 t 1 5 - 4 6 5 1 . x a m y c n e u q e r f t u p t u o d e g n a h c n o i t c e s s e r u t a e f d n a n o i t p i r c s e d l a r e n e g . z h m 5 2 . 1 3 o t z h m 0 4 m o r f . x a m z h m 5 2 . 1 3 o t . x a m z h m 0 4 m o r f y c n e u q e r f t u p t u o d e g n a h c - s e l b a t c a . t o l p e s i o n e s a h p d e d d a g n i k r a m e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 8 0 / 8 / 0 1
ics81006i vcxo-to-6 lvcmos outputs innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt for tech support netcom@idt.com +480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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